Mangalore
homeKarnataka coast. Where the two rivers meet the Arabian Sea and nothing moves faster than it needs to. Grew up here, came back here. The coffee is filter, the fish is fresh, and sunset at Panambur is the only standup I'd never skip.
Hi — I'm Nidhi. From the coast, in the cloud.
DevOps engineer from Mangalore. Two years at Kyndryl in Bengaluru on Jenkins pipelines and AWS infrastructure for a fintech client, then an MSc in Microelectronic Systems at the University of Liverpool. Home now on the Karnataka coast, back on proper coffee, and looking for the next build to break and fix.
Two coastlines
Liverpool
one yearA year on the Mersey for the MSc. Learned that four seasons fit in one afternoon, that sound is a complete sentence, and that a city built on a river understands rollback better than most release managers.
Bengaluru sits between the two — two years at Kyndryl, 100+ pipelines, and the on-call rota that taught me more than either degree.
Work
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Associate DevOps Engineer
Kyndryl
Jul 2023 — Aug 2025 Bengaluru, India- Built and maintained 100+ Jenkins CI/CD pipelines (Groovy) for build, deployment, batch and cron jobs, integrating SonarQube quality gates, Snyk dependency scans and Nexus artifact storage; supported weekly and monthly releases.
- Managed AWS infrastructure across 4 environments (build, QA, staging, production) including EC2, VPC, IAM, Auto Scaling Groups, Load Balancers, S3 and CloudWatch.
- Automated infrastructure provisioning with Terraform across all 4 environments, cutting environment setup time by ~60% and eliminating manual configuration errors.
- Supported 10 microservices on Amazon EKS — image builds, cluster configuration and workload troubleshooting — with structured rollout and rollback procedures to minimise deployment risk.
- Troubleshot incidents on Linux EC2 instances and EKS nodes via SSH, raised through Jira and ServiceNow and resolved within SLA — checking services (
systemctl), logs (journalctl), disk usage (df,du) and processes. - Implemented YAML-based Azure DevOps pipelines for a .NET application (build, test, packaging), using ARM templates to provision Azure resources and deploying artifacts to IBM HTTP Server environments.
- Delivered AI/GenAI PoCs (Battery Management System and ITSM analytics) with containerised inference pipelines using NVIDIA CUDA, NGC/NIM and Triton Inference Server; prototyped LLM-based agents for internal automation.
- Supported infrastructure and pipeline delivery for a fintech client, working to financial-sector compliance and enterprise deployment standards.
Two years of production on-call teaches you things a course can't: that the fix is usually boring, that the runbook is always out of date, and that the incident always starts at 4 p.m. on a Friday.
Education
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MSc — Microelectronic Systems
University of Liverpool
Sep 2025 — Sep 2026 Liverpool, UKDigital and embedded systems design, RISC-V architecture, VLSI and low-power circuit design, verification with Verilog and SystemVerilog.
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BE — Electronics & Communication
Sahyadri College of Engineering & Management (VTU)
Aug 2019 — Jul 2023 Mangalore, India -
Certifications
Microsoft · AWS · HashiCorp · REVA
AZ-104Azure Administrator AssociateMicrosoft
CCPAWS Certified Cloud PractitionerAWS- AI-900Azure AI FundamentalsMicrosoft
003Terraform AssociateHashiCorp- AZ-900Azure FundamentalsMicrosoft
AICertified AI EngineerREVA Academy (Kyndryl)
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Publication
IEEE ICICACS 2023 · Scopus indexed
Analysis of High-Performance Low Power Full Adder Circuit. View DOI ↗
Skills
Cloud & Infrastructure
- AWS
- EKS
- EC2
- VPC
- IAM
- RDS
- ElastiCache
- Azure
- AKS
- Entra ID
- Key Vault
Terraform- ARM templates
- Bicep
Ansible
Linux
DevOps & CI/CD
Jenkins
GitHub Actions- Azure DevOps
ArgoCD
Kustomize
Helm
Docker- Kubernetes
Git
Python
Bash- Groovy
Jira- ServiceNow
DevSecOps
- Semgrep
SonarQube
Snyk
Trivy- Burp Suite
- Gitleaks
- Kyverno
- IRSA
- External Secrets
- cert-manager
- Nexus
Observability & Data
Prometheus
Grafana- Loki
- Alertmanager
- CloudWatch
Kafka
Redis
PostgreSQL
AI / ML
NVIDIA CUDA- NGC / NIM
- Triton Inference Server
- LLM agents
- RAG
Hardware
- Verilog
- SystemVerilog
- RISC-V
- VLSI design
- Quartus
- MATLAB
The hardware row isn't filler. Knowing what happens below the kernel makes you better at the layers above it — you stop treating latency, memory and heat as someone else's problem.
Projects
Also on GitHub
- Backstage_VRN Internal developer portal — service catalogue and scaffolding
- backstage-templates Terraform-backed software templates for self-service provisioning
- Incident_Remediation Automated remediation for common production incidents
- Platform_Engg Platform engineering experiments and tooling
- yaml-ci-cd-dataset A dataset of CI/CD pipeline definitions for analysis
- Async-FIFO-Verilog Clock-domain-crossing FIFO in Verilog
Plus a published paper — Analysis of High-Performance Low Power Full Adder Circuit, IEEE ICICACS 2023, Scopus indexed. DOI ↗